Multiprocessor architectures enable processing systems to scale with demand simply by adding additional processors. As such, multiprocessor architectures are popular solutions for growing businesses that require scalable solutions to absorb increased transaction volume. Multiprocessor architectures may be implemented to realize network processors, web servers, database servers, and the like.
FIG. 1A illustrates a known symmetric multi-processing (“SMP”) architecture 100A. SMP architecture 100A includes multiple processors that are coupled in parallel via an electrical interconnect to a single pool of shared memory. Known SMP architectures range from two processors sharing memory to as many as thirty-two or more. Generally, one processor is designated as the boot processor that loads an operating system (“OS”) from an attached storage device into the shared memory. Once the OS is loaded, the other processors are brought online. Typically, SMP architecture 100A maintains a single OS instance and a single instance of each application in shared memory. The processors are used as a pool of processing resources, all of which may be processing at a given time or waiting in an idle loop to be assigned a task. SMP architecture 100A is faster than a unitary processing system because each processor can be assigned to execute a different application in parallel, or if the applications are multithreaded, multiple processors can be assigned to execute each thread of a multithreaded application.
SMP architecture 100A is scalable by simply plugging in additional processors. As the number of processors increase so to does the number of applications or threads that may be simultaneously executed in parallel.
FIG. 1B illustrates a known massively parallel processing (“MPP”) architecture 100B. MPP architecture 100B is different from SMP 100A in that each processor is coupled to its own local memory and maintains its own instance of an OS and applications it is executing. MPP architecture 100B uses a different multiprocessing paradigm than SMP architecture 100A. MPP architecture 100B divides a large task into subtasks that can be solved simultaneously. The results of the subtasks are then shared over a high-speed electrical interconnect. In order to leverage the parallel processing power of MPP architecture 100B, a large problem must be susceptible to a divide and conquer approach.
Other solutions include coupling multiple processors in a point-to-point configuration where each processor is directly coupled to each of the other processors. While these configurations are able to provide the desired interconnect bandwidth, the configurations are complex, requiring multiple electrical interconnect buses.